Instructor                          Prof.A.Pal (apal@cse.iitkgp.ernet.in)

            Timing                               Slot F [Wednesday(9:30-10:25) ,Thursday(8:30-9:25), Friday(10:30-12:25)]

            Venue                               Room No. 108 (Department of Computer Science and Engineering)

            Teaching Assintants           Bibhas Ghoshal (bibhas.ghoshal@gmail.com) and  Subhadip Kundu(dip224@gmail.com )

             Course outline                    

                   A  tentative  course outline is provided here. For detailed course syllabus referr to the  official site

                   1. Basics of MOS circuits: MOS Transistor structure and device modeling,MOS inverters and MOS Combinational Circuits

                   2. Sources of power dissipation: Dynamic Power Dissipation,Static Power Dissipation and Degrees of Freedom

                   3. Supply Voltage Scaling Approaches:Device feature size scaling,Multi-Vdd Circuits, Architectural level approaches

                       High-level transformations,Dynamic voltage scaling and Power Management

                   4. Switched Capacitance Minimization Approaches: Hw/ Sw Tradeoff, Bus Encoding,2's complement Vs Sign Magnitude

                       Architectural optimization, Clock Gating and Logic styles

                   5. Leakage Power minimization Approaches:  VTCMOS, MTCMOS, DTCMOS and Transistor stacking

                   6. Special Topics:Adiabatic Switching Circuits, Battery-aware Synthesis and Variation tolerant design

              References

                    1. Sung_Mo Kang, Yusuf Leblebici, CMOS Digital Integrated Circuits, Tata Mcgraw Hill

                  2. Neil H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design, 2nd Edition, Addison Wesley (Indian reprint).

                  3. A. Bellamour, and M. I. Elmasri, Low Power VLSI CMOS Circuit Design, Kluwer Academic Press, 1995

                  4. Anantha P. Chandrakasan and Robert W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995

                  5. Neil Weste, David Harris, "CMOS VLSI Design: A Circuits and Systems Perspective" Pearson Education , 2004

             Grading Scheme                        

                  The final grading will be based on the following rule

                  End semester(50% weightage), Mid semester(30% weightage) and Term Assessment(20% weightage)

                 Note: Term Assessment will include two class tests, assignments given, attendance and class performance

     Announcements

                   You are expected to check this place regularly for reference material for the course .

                   Download reference material for the topics covered after mid-semester.

                   Marks of class test1 and Mid-semster

            Class                                        

                   The first theoretical class is on 05-01-2011

             Links                                        

                   Follow the vtvt website for a tutorial on Hspice.

                   You are required to use the spice files and the model files used in the tutorial for the assignments.